The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, while transistors have scaled down considerably between generations, passive devices (e.g., resistors, capacitors, inductors, etc.) have not always progressed as quickly. In many cases, the simple physics of these devices pose a substantial roadblock. For example, even with improved materials, shrinking a capacitor or inductor often reduces capacitance or inductance far more than the improved materials can compensate.
In addition to device size, for passive devices that are not formed on the same substrate as the active circuit devices, the manner in which the passive devices are connected may have a significant impact on the size of the finished circuit. In a common example, passive devices and active devices are mounted on a printed circuit board (PCB). Conductive traces on the PCB electrically coupled the various devices. However, PCB traces may be bulky, and the density of devices on the PCB may be low in order to leave room to solder.
To prevent passive devices from having an outsized effect on a circuit footprint, further developments in passive device layout and fabrication are needed. In particular, improvements to device formation and bonding that reduce device and routing area while increasing reliability would be extremely beneficial. Accordingly, while existing passive circuit devices have been generally adequate, the potential for future improvements still exists.